A 5.61 pJ, 16 kb 9T SRAM with single-ended equalized bitlines and fast local write-back for cell stability improvement
A 5.61 pJ, 16 kb 9T SRAM is implemented in 65nm CMOS technology. A single-ended equalized bitline scheme is proposed to improve both read bitline voltage swing and sensing timing window. A fast local write-back allows the half-select-free write operation without performance degradation. The test chi...
| Main Authors: | , , |
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| Other Authors: | |
| Format: | Conference Paper |
| Language: | English |
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2013
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| Online Access: | https://hdl.handle.net/10356/99838 http://hdl.handle.net/10220/16227 |
| _version_ | 1826125691337310208 |
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| author | Li, Qi Wang, Bo Kim, Tony Tae-Hyoung |
| author2 | School of Electrical and Electronic Engineering |
| author_facet | School of Electrical and Electronic Engineering Li, Qi Wang, Bo Kim, Tony Tae-Hyoung |
| author_sort | Li, Qi |
| collection | NTU |
| description | A 5.61 pJ, 16 kb 9T SRAM is implemented in 65nm CMOS technology. A single-ended equalized bitline scheme is proposed to improve both read bitline voltage swing and sensing timing window. A fast local write-back allows the half-select-free write operation without performance degradation. The test chip shows a minimum operating voltage of 0.24V and a minimum energy of 5.61pJ at 0.3V. |
| first_indexed | 2024-10-01T06:40:29Z |
| format | Conference Paper |
| id | ntu-10356/99838 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2024-10-01T06:40:29Z |
| publishDate | 2013 |
| record_format | dspace |
| spelling | ntu-10356/998382020-03-07T13:24:49Z A 5.61 pJ, 16 kb 9T SRAM with single-ended equalized bitlines and fast local write-back for cell stability improvement Li, Qi Wang, Bo Kim, Tony Tae-Hyoung School of Electrical and Electronic Engineering European Solid State Device Research Conference (2012 : 42th) DRNTU::Engineering::Electrical and electronic engineering A 5.61 pJ, 16 kb 9T SRAM is implemented in 65nm CMOS technology. A single-ended equalized bitline scheme is proposed to improve both read bitline voltage swing and sensing timing window. A fast local write-back allows the half-select-free write operation without performance degradation. The test chip shows a minimum operating voltage of 0.24V and a minimum energy of 5.61pJ at 0.3V. 2013-10-03T03:00:31Z 2019-12-06T20:12:12Z 2013-10-03T03:00:31Z 2019-12-06T20:12:12Z 2012 2012 Conference Paper Li, Q., Wang, B., & Kim, T. T. (2012). A 5.61 pJ, 16 kb 9T SRAM with single-ended equalized bitlines and fast local write-back for cell stability improvement. ESSDERC 2012 - 42nd European Solid State Device Research Conference, pp.201-204. https://hdl.handle.net/10356/99838 http://hdl.handle.net/10220/16227 10.1109/ESSDERC.2012.6343368 en |
| spellingShingle | DRNTU::Engineering::Electrical and electronic engineering Li, Qi Wang, Bo Kim, Tony Tae-Hyoung A 5.61 pJ, 16 kb 9T SRAM with single-ended equalized bitlines and fast local write-back for cell stability improvement |
| title | A 5.61 pJ, 16 kb 9T SRAM with single-ended equalized bitlines and fast local write-back for cell stability improvement |
| title_full | A 5.61 pJ, 16 kb 9T SRAM with single-ended equalized bitlines and fast local write-back for cell stability improvement |
| title_fullStr | A 5.61 pJ, 16 kb 9T SRAM with single-ended equalized bitlines and fast local write-back for cell stability improvement |
| title_full_unstemmed | A 5.61 pJ, 16 kb 9T SRAM with single-ended equalized bitlines and fast local write-back for cell stability improvement |
| title_short | A 5.61 pJ, 16 kb 9T SRAM with single-ended equalized bitlines and fast local write-back for cell stability improvement |
| title_sort | 5 61 pj 16 kb 9t sram with single ended equalized bitlines and fast local write back for cell stability improvement |
| topic | DRNTU::Engineering::Electrical and electronic engineering |
| url | https://hdl.handle.net/10356/99838 http://hdl.handle.net/10220/16227 |
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