Design of a current comparator for quaternary multi valued analog to digital converter
A low-power quaternary comparator circuit using current-mode CMOS multiple-valued logic (MVL) circuits has been presented in this paper. Existing MVL comparator circuits consume high power. The circuit presented in this paper has been shown low power digital output. It has been simulated with PSPICE...
| Main Authors: | , , , |
|---|---|
| Format: | Proceeding Paper |
| Language: | English |
| Published: |
2011
|
| Subjects: | |
| Online Access: | http://irep.iium.edu.my/11857/1/Design_of_a_current_comparator_for_quaternary_multi_valued_analog_to_digital_converter.pdf |
| Summary: | A low-power quaternary comparator circuit using current-mode CMOS multiple-valued logic (MVL) circuits has been presented in this paper. Existing MVL comparator circuits consume high power. The circuit presented in this paper has been shown low power digital output. It has been simulated with PSPICE using the transistor model parameter values of the BSIM3 NMOS model V3.2 for 0.13 μm CMOS process. With a 1.3-volt power supply, simulations show that the proposed quaternary comparator consumes 0.107 mW total average static power and a sampling rate 500MHz. Power and speed for comparators designed in these technologies are discussed. The comparator design is suitable for the needs of mixed-signal integrated circuit design and can be implemented as a conversion circuit for systems based on multiple-valued logic design. |
|---|