IMPLEMENTASI PADA FPGA ATAS ESTIMATOR HALUS DAN INTERPOLATOR DENGAN PENGALI BERBASIS UNTAI SEKUENSIAL UNTUK ESTIMASI KANAL OFDM
Orthogonal Frequency Division Multiplexing (OFDM) is a parallel data transmission scheme which is able to provide bandwidth eficiency and high bit rate. The existence of multipath fading in wireless communication cause ISI (Inter Simbol Interference) that implies the needs of smooth estimator and in...
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| Format: | Thesis |
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[Yogyakarta] : Universitas Gadjah Mada
2013
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| _version_ | 1826047654023397376 |
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| author | , NOVIA WULANDARI , Ir. Budi Setiyanto, MT. |
| author_facet | , NOVIA WULANDARI , Ir. Budi Setiyanto, MT. |
| author_sort | , NOVIA WULANDARI |
| collection | UGM |
| description | Orthogonal Frequency Division Multiplexing (OFDM) is a parallel data transmission scheme which is able to provide bandwidth eficiency and high bit rate. The existence of multipath fading in wireless communication cause ISI (Inter Simbol Interference) that implies the needs of smooth estimator and interpolator in OFDM receiver. Channel estimator with pilot simbol helps OFDM system to estimate channel characteristic. Sending a lot of pilot symbol will decrease the throughput. Limitation of pilot�s usage can be done by sending pilot symbol in certain subchannel, while subchannel that do not have pilot symbol will be estimated using interpolator.
FPGA (Field Programmable Gate Array) is one of programmable device for digital system. FPGA is one of the devices that can be used to implement the smooth estimator and interpolator for channel equalizer. HDL (Hardware Description Language) is a language that is used to programing FPGA. The most popular HDL is VHDL (Very high speed integrated circuit Hardware Description Language).
As a result, the implementation of cascaded smooth estimator and interpolator is able to show true performance and the output is agree with the result of Microsoft Excel. In terms of capacity, smooth estimator and interpolator design needs 2,276 slices and the maximum clock is 177,999 MHz. |
| first_indexed | 2024-03-13T23:14:18Z |
| format | Thesis |
| id | oai:generic.eprints.org:126570 |
| institution | Universiti Gadjah Mada |
| last_indexed | 2024-03-13T23:14:18Z |
| publishDate | 2013 |
| publisher | [Yogyakarta] : Universitas Gadjah Mada |
| record_format | dspace |
| spelling | oai:generic.eprints.org:1265702016-03-04T08:41:09Z https://repository.ugm.ac.id/126570/ IMPLEMENTASI PADA FPGA ATAS ESTIMATOR HALUS DAN INTERPOLATOR DENGAN PENGALI BERBASIS UNTAI SEKUENSIAL UNTUK ESTIMASI KANAL OFDM , NOVIA WULANDARI , Ir. Budi Setiyanto, MT. ETD Orthogonal Frequency Division Multiplexing (OFDM) is a parallel data transmission scheme which is able to provide bandwidth eficiency and high bit rate. The existence of multipath fading in wireless communication cause ISI (Inter Simbol Interference) that implies the needs of smooth estimator and interpolator in OFDM receiver. Channel estimator with pilot simbol helps OFDM system to estimate channel characteristic. Sending a lot of pilot symbol will decrease the throughput. Limitation of pilot�s usage can be done by sending pilot symbol in certain subchannel, while subchannel that do not have pilot symbol will be estimated using interpolator. FPGA (Field Programmable Gate Array) is one of programmable device for digital system. FPGA is one of the devices that can be used to implement the smooth estimator and interpolator for channel equalizer. HDL (Hardware Description Language) is a language that is used to programing FPGA. The most popular HDL is VHDL (Very high speed integrated circuit Hardware Description Language). As a result, the implementation of cascaded smooth estimator and interpolator is able to show true performance and the output is agree with the result of Microsoft Excel. In terms of capacity, smooth estimator and interpolator design needs 2,276 slices and the maximum clock is 177,999 MHz. [Yogyakarta] : Universitas Gadjah Mada 2013 Thesis NonPeerReviewed , NOVIA WULANDARI and , Ir. Budi Setiyanto, MT. (2013) IMPLEMENTASI PADA FPGA ATAS ESTIMATOR HALUS DAN INTERPOLATOR DENGAN PENGALI BERBASIS UNTAI SEKUENSIAL UNTUK ESTIMASI KANAL OFDM. UNSPECIFIED thesis, UNSPECIFIED. http://etd.ugm.ac.id/index.php?mod=penelitian_detail&sub=PenelitianDetail&act=view&typ=html&buku_id=66797 |
| spellingShingle | ETD , NOVIA WULANDARI , Ir. Budi Setiyanto, MT. IMPLEMENTASI PADA FPGA ATAS ESTIMATOR HALUS DAN INTERPOLATOR DENGAN PENGALI BERBASIS UNTAI SEKUENSIAL UNTUK ESTIMASI KANAL OFDM |
| title | IMPLEMENTASI PADA FPGA ATAS ESTIMATOR HALUS DAN INTERPOLATOR DENGAN PENGALI BERBASIS UNTAI SEKUENSIAL UNTUK ESTIMASI KANAL OFDM |
| title_full | IMPLEMENTASI PADA FPGA ATAS ESTIMATOR HALUS DAN INTERPOLATOR DENGAN PENGALI BERBASIS UNTAI SEKUENSIAL UNTUK ESTIMASI KANAL OFDM |
| title_fullStr | IMPLEMENTASI PADA FPGA ATAS ESTIMATOR HALUS DAN INTERPOLATOR DENGAN PENGALI BERBASIS UNTAI SEKUENSIAL UNTUK ESTIMASI KANAL OFDM |
| title_full_unstemmed | IMPLEMENTASI PADA FPGA ATAS ESTIMATOR HALUS DAN INTERPOLATOR DENGAN PENGALI BERBASIS UNTAI SEKUENSIAL UNTUK ESTIMASI KANAL OFDM |
| title_short | IMPLEMENTASI PADA FPGA ATAS ESTIMATOR HALUS DAN INTERPOLATOR DENGAN PENGALI BERBASIS UNTAI SEKUENSIAL UNTUK ESTIMASI KANAL OFDM |
| title_sort | implementasi pada fpga atas estimator halus dan interpolator dengan pengali berbasis untai sekuensial untuk estimasi kanal ofdm |
| topic | ETD |
| work_keys_str_mv | AT noviawulandari implementasipadafpgaatasestimatorhalusdaninterpolatordenganpengaliberbasisuntaisekuensialuntukestimasikanalofdm AT irbudisetiyantomt implementasipadafpgaatasestimatorhalusdaninterpolatordenganpengaliberbasisuntaisekuensialuntukestimasikanalofdm |