PEMBALIK KOMPLEKS 8-BIT BERBASIS PENGALI DAN PEMBAGI SEKUENSIAL MENGGUNAKAN FPGA XILINX SPARTAN 3E UNTUK PENYAMAAN KANAL OFDM - , NICOLAS ARYA K, Ir. Budi Setiyanto, M.T. ([Yogyakarta] : Universitas Gadjah Mada, 2014)
OFDM receiver needs a channel equalizer (CE) to gain similarity between received signals and transmitted signals. CE multiplies received signal with a weighting factor which results a signal similar with transmitted signal. Weighting factor is reciprocal of the channel estimator output, which become the multiplier factor in CE. This research offered a reciprocal circuit to process the output from estimator and interpolator blocks yield OFDM CE weighting factor. There are two reciprocal circuit designs in this research. They are reciprocal without internal bit scaling (system A), and reciprocal with internal bit scaling (system B). Reciprocal circuits in this research is four sub-channels circuit, with sequential multiplier and sequential divider. The circuits are designed with VHDL (Very high speed integrated circuit Hardware Description Language) and Xilinx ISE 12i sofware. Design result and simulation show that system A needs 2,279 slices of FPGA resource and 609.876 ns delay. In the other hand, system B needs 1,136 slices of FPGA resource and 262.06 ns delay.