Development of an economical lapping process

The manufacturing of silicon wafers in particular involves numerous processes such as grinding, lapping, and polishing of large diameter wafers employing expensive equipment in order to produce the required optical quality and damage-free surfaces. In the finishing of thin silicon chips for making I...

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Main Authors: Konneh, Mohamed, Tamsir, Afzeri, Triblas Adesta, Erry Yulian
Format: Article
Language:English
Published: Trans Tech Publications, Switzerland 2012
Subjects:
Online Access:http://irep.iium.edu.my/28463/2/DEVELOPMENT_OF_AN_ECONOMICAL_LAPPING_PROCESS.pdf
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author Konneh, Mohamed
Tamsir, Afzeri
Triblas Adesta, Erry Yulian
author_facet Konneh, Mohamed
Tamsir, Afzeri
Triblas Adesta, Erry Yulian
author_sort Konneh, Mohamed
collection IIUM
description The manufacturing of silicon wafers in particular involves numerous processes such as grinding, lapping, and polishing of large diameter wafers employing expensive equipment in order to produce the required optical quality and damage-free surfaces. In the finishing of thin silicon chips for making IC chips especially, it is difficult to lap and polish the substrate and obtain low surface integrity, surface finish and at the same time generate flat planar surfaces. This paper presents the development of a low cost lapping process, the process tried out on thin silicon chips that generated fracture-free with mirror-like surfaces of low roughness values and reasonably high degree of flatness.
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spelling oai:generic.eprints.org:284632015-08-18T06:15:58Z http://irep.iium.edu.my/28463/ Development of an economical lapping process Konneh, Mohamed Tamsir, Afzeri Triblas Adesta, Erry Yulian TJ1125 Machine shops and machine shop practice The manufacturing of silicon wafers in particular involves numerous processes such as grinding, lapping, and polishing of large diameter wafers employing expensive equipment in order to produce the required optical quality and damage-free surfaces. In the finishing of thin silicon chips for making IC chips especially, it is difficult to lap and polish the substrate and obtain low surface integrity, surface finish and at the same time generate flat planar surfaces. This paper presents the development of a low cost lapping process, the process tried out on thin silicon chips that generated fracture-free with mirror-like surfaces of low roughness values and reasonably high degree of flatness. Trans Tech Publications, Switzerland 2012 Article PeerReviewed application/pdf en http://irep.iium.edu.my/28463/2/DEVELOPMENT_OF_AN_ECONOMICAL_LAPPING_PROCESS.pdf Konneh, Mohamed and Tamsir, Afzeri and Triblas Adesta, Erry Yulian (2012) Development of an economical lapping process. Advanced Materials Research, 472-47. pp. 2348-2353. ISSN 1022-6680 http://www.scientific.net/AMR.472-475.2348
spellingShingle TJ1125 Machine shops and machine shop practice
Konneh, Mohamed
Tamsir, Afzeri
Triblas Adesta, Erry Yulian
Development of an economical lapping process
title Development of an economical lapping process
title_full Development of an economical lapping process
title_fullStr Development of an economical lapping process
title_full_unstemmed Development of an economical lapping process
title_short Development of an economical lapping process
title_sort development of an economical lapping process
topic TJ1125 Machine shops and machine shop practice
url http://irep.iium.edu.my/28463/2/DEVELOPMENT_OF_AN_ECONOMICAL_LAPPING_PROCESS.pdf
work_keys_str_mv AT konnehmohamed developmentofaneconomicallappingprocess
AT tamsirafzeri developmentofaneconomicallappingprocess
AT triblasadestaerryyulian developmentofaneconomicallappingprocess