Reconfiguration and Yield of a Hierarchical Torus Network
This paper presents the reconfiguration and yield of a new interconnection network, Hierarchical Torus Network (HTN). A HTN is a 2D-torus network of multiple basic modules, in which the basic modules are 3D-torus networks that are hierarchically interconnected for higher level networks. The static n...
| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
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Medknow publication
2013
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| Online Access: | http://irep.iium.edu.my/29810/1/IETETechRev_2013.pdf |
| _version_ | 1825647257598296064 |
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| author | Rahman, M.M. Hafizur Fukushi, Masaru Inoguchi, Yasushi |
| author_facet | Rahman, M.M. Hafizur Fukushi, Masaru Inoguchi, Yasushi |
| author_sort | Rahman, M.M. Hafizur |
| collection | IIUM |
| description | This paper presents the reconfiguration and yield of a new interconnection network, Hierarchical Torus Network (HTN). A HTN is a 2D-torus network of multiple basic modules, in which the basic modules are 3D-torus networks that are hierarchically interconnected for higher level networks. The static network performance and dynamic communication performance under dimension- order routing of the HTN have already been studied and network performances are good. However, the fault tolerance performance of the HTN has not yet been evaluated. The goal of this paper is to derive a theoretical estimate of system yield for the HTN as a function of defect density with a reconfiguration approach by hardware redundancy. Yield is the probability of obtaining a fault free network. Despite the dramatic improvement in fault tolerance in recent years, it is still necessary to provide redundancy and fault circumvention to achieve efficient system yield for large multicomputer systems. Thus, we provide redundant hardware to reconfigure the faulty nodes, switches, and links to healthy nodes, switches, and links. The results indicate that with a 25% redundancy the yield of the HTN is satisfactory. We also discuss the 3D-WSI implementation issue and show that HTN permits efficient VLSI/ULSI/WSI realization due to the fewer numbers of vertical links between the silicon wafers. The longest wire has a length of 4.5 cm which represents 4.20 times improvement over the planar implementation. |
| first_indexed | 2024-03-05T23:14:58Z |
| format | Article |
| id | oai:generic.eprints.org:29810 |
| institution | International Islamic University Malaysia |
| language | English |
| last_indexed | 2024-03-05T23:14:58Z |
| publishDate | 2013 |
| publisher | Medknow publication |
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| spelling | oai:generic.eprints.org:298102013-05-24T10:09:03Z http://irep.iium.edu.my/29810/ Reconfiguration and Yield of a Hierarchical Torus Network Rahman, M.M. Hafizur Fukushi, Masaru Inoguchi, Yasushi TK Electrical engineering. Electronics Nuclear engineering This paper presents the reconfiguration and yield of a new interconnection network, Hierarchical Torus Network (HTN). A HTN is a 2D-torus network of multiple basic modules, in which the basic modules are 3D-torus networks that are hierarchically interconnected for higher level networks. The static network performance and dynamic communication performance under dimension- order routing of the HTN have already been studied and network performances are good. However, the fault tolerance performance of the HTN has not yet been evaluated. The goal of this paper is to derive a theoretical estimate of system yield for the HTN as a function of defect density with a reconfiguration approach by hardware redundancy. Yield is the probability of obtaining a fault free network. Despite the dramatic improvement in fault tolerance in recent years, it is still necessary to provide redundancy and fault circumvention to achieve efficient system yield for large multicomputer systems. Thus, we provide redundant hardware to reconfigure the faulty nodes, switches, and links to healthy nodes, switches, and links. The results indicate that with a 25% redundancy the yield of the HTN is satisfactory. We also discuss the 3D-WSI implementation issue and show that HTN permits efficient VLSI/ULSI/WSI realization due to the fewer numbers of vertical links between the silicon wafers. The longest wire has a length of 4.5 cm which represents 4.20 times improvement over the planar implementation. Medknow publication 2013-04-15 Article PeerReviewed application/pdf en http://irep.iium.edu.my/29810/1/IETETechRev_2013.pdf Rahman, M.M. Hafizur and Fukushi, Masaru and Inoguchi, Yasushi (2013) Reconfiguration and Yield of a Hierarchical Torus Network. IETE Technical Review, 30 (2). pp. 120-128. ISSN 0256-4602 (P); 0974-5971 (O) http://tr.ietejournals.org/temp/IETETechRev302120-3690409_101504.pdf |
| spellingShingle | TK Electrical engineering. Electronics Nuclear engineering Rahman, M.M. Hafizur Fukushi, Masaru Inoguchi, Yasushi Reconfiguration and Yield of a Hierarchical Torus Network |
| title | Reconfiguration and Yield of a Hierarchical Torus Network |
| title_full | Reconfiguration and Yield of a Hierarchical Torus Network |
| title_fullStr | Reconfiguration and Yield of a Hierarchical Torus Network |
| title_full_unstemmed | Reconfiguration and Yield of a Hierarchical Torus Network |
| title_short | Reconfiguration and Yield of a Hierarchical Torus Network |
| title_sort | reconfiguration and yield of a hierarchical torus network |
| topic | TK Electrical engineering. Electronics Nuclear engineering |
| url | http://irep.iium.edu.my/29810/1/IETETechRev_2013.pdf |
| work_keys_str_mv | AT rahmanmmhafizur reconfigurationandyieldofahierarchicaltorusnetwork AT fukushimasaru reconfigurationandyieldofahierarchicaltorusnetwork AT inoguchiyasushi reconfigurationandyieldofahierarchicaltorusnetwork |