Network-on-chip implementation of hierarchical torus network - Rahman, M.M. Hafizur; Ray, Sajib; Md. , Rabiul Awal (2013)
The interconnection network plays an important role in the performance and energy consumption of a Network-on-Chip (NoC) system. In this paper, we implement the NoC implementation of hierarchical torus network. The Hierarchical Torus Network (HTN) is a hierarchical interconnection network consisting of multiple BM that is hierarchically interconnected for higher-level networks. The number of layers needed for routing the links in HTN level-2 is shown to be bounded at 8, which is feasible to be implemented with current and future VLSI technologies. With the innovative hierarchical structure, HTN possesses the following features: hierarchical structure, smaller diameter and average distance, embedded mesh/torus topology, a constant node degree of 8. These features make HTN a promising solution for the interconnection network of NoC designs satisfying the requirements for scalability, energy efficiency, customizable, and fault-tolerance.