Verilog-A compact modelling of SiC devices with Qucs-S, QucsStudio and MAPP/Octave FOSS tools
Qucs-S is a spin-off of the Qucs cross-platform circuit simulator. "S" letter indicates SPICE. The purpose of the Qucs-S subproject is to use free SPICE circuit simulation kernels with the Qucs GUI. It merges the power of SPICE and the simplicity of the Qucs GUI. Qucs intentionally uses it...
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| Format: | Conference or Workshop Item |
| Language: | English |
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2018
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| Online Access: | https://repository.londonmet.ac.uk/3986/1/MEB_EDSDLMQL_2018.pdf |
| _version_ | 1825625234006343680 |
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| author | Brinson, Mike |
| author_facet | Brinson, Mike |
| author_sort | Brinson, Mike |
| collection | LMU |
| description | Qucs-S is a spin-off of the Qucs cross-platform circuit simulator. "S" letter indicates SPICE. The purpose of the Qucs-S subproject is to use free SPICE circuit simulation kernels with the Qucs GUI. It merges the power of SPICE and the simplicity of the Qucs GUI. Qucs intentionally uses its own SPICE incompatible simulation kernel Qucsator. It has advanced RF and AC domain simulation features, but most of the existing industrial SPICE models are incompatible with it. Qucs-S is not a simulator by itself, but it requires to use a simulation backend with it. The schematic document format of Qucs and Qucs-S are fully compatible. Qucs-S allows to use the following simulation kernels with it:
Ngspice is recommended to use. Ngspice is powerful mixed-level/mixed-signal circuit simulator. The most of industrial SPICE models are compatible with Ngspice. It has an excellent performance for time-domain simulation of switching circuits and powerful postprocessor.
XYCE is a new SPICE-compatible circuit simulator written by Sandia from the scratch. It supports basic SPICE simulation types and has an advanced RF simulation features such as Harmonic balance simulation.
SpiceOpus is developed by the Faculty of Electrical Engineering of the Ljubljana University. It based on the SPICE-3f5 code Qucsator as backward compatible. |
| first_indexed | 2024-07-09T03:55:44Z |
| format | Conference or Workshop Item |
| id | oai:repository.londonmet.ac.uk:3986 |
| institution | London Metropolitan University |
| language | English |
| last_indexed | 2024-07-09T03:55:44Z |
| publishDate | 2018 |
| record_format | eprints |
| spelling | oai:repository.londonmet.ac.uk:39862018-11-26T15:11:46Z https://repository.londonmet.ac.uk/3986/ Verilog-A compact modelling of SiC devices with Qucs-S, QucsStudio and MAPP/Octave FOSS tools Brinson, Mike 620 Engineering & allied operations Qucs-S is a spin-off of the Qucs cross-platform circuit simulator. "S" letter indicates SPICE. The purpose of the Qucs-S subproject is to use free SPICE circuit simulation kernels with the Qucs GUI. It merges the power of SPICE and the simplicity of the Qucs GUI. Qucs intentionally uses its own SPICE incompatible simulation kernel Qucsator. It has advanced RF and AC domain simulation features, but most of the existing industrial SPICE models are incompatible with it. Qucs-S is not a simulator by itself, but it requires to use a simulation backend with it. The schematic document format of Qucs and Qucs-S are fully compatible. Qucs-S allows to use the following simulation kernels with it: Ngspice is recommended to use. Ngspice is powerful mixed-level/mixed-signal circuit simulator. The most of industrial SPICE models are compatible with Ngspice. It has an excellent performance for time-domain simulation of switching circuits and powerful postprocessor. XYCE is a new SPICE-compatible circuit simulator written by Sandia from the scratch. It supports basic SPICE simulation types and has an advanced RF simulation features such as Harmonic balance simulation. SpiceOpus is developed by the Faculty of Electrical Engineering of the Ljubljana University. It based on the SPICE-3f5 code Qucsator as backward compatible. 2018-06-20 Conference or Workshop Item PeerReviewed text en cc_by_nd https://repository.londonmet.ac.uk/3986/1/MEB_EDSDLMQL_2018.pdf Brinson, Mike (2018) Verilog-A compact modelling of SiC devices with Qucs-S, QucsStudio and MAPP/Octave FOSS tools. In: IEEE EDS Mini-Colloquium, 20 June 2018, Gdynia, Poland. |
| spellingShingle | 620 Engineering & allied operations Brinson, Mike Verilog-A compact modelling of SiC devices with Qucs-S, QucsStudio and MAPP/Octave FOSS tools |
| title | Verilog-A compact modelling of SiC devices with Qucs-S, QucsStudio and MAPP/Octave FOSS tools |
| title_full | Verilog-A compact modelling of SiC devices with Qucs-S, QucsStudio and MAPP/Octave FOSS tools |
| title_fullStr | Verilog-A compact modelling of SiC devices with Qucs-S, QucsStudio and MAPP/Octave FOSS tools |
| title_full_unstemmed | Verilog-A compact modelling of SiC devices with Qucs-S, QucsStudio and MAPP/Octave FOSS tools |
| title_short | Verilog-A compact modelling of SiC devices with Qucs-S, QucsStudio and MAPP/Octave FOSS tools |
| title_sort | verilog a compact modelling of sic devices with qucs s qucsstudio and mapp octave foss tools |
| topic | 620 Engineering & allied operations |
| url | https://repository.londonmet.ac.uk/3986/1/MEB_EDSDLMQL_2018.pdf |
| work_keys_str_mv | AT brinsonmike verilogacompactmodellingofsicdeviceswithqucssqucsstudioandmappoctavefosstools |