Synchronous protocol automata: a framework for modelling and verification of SoC communication architectures
Plug-n-play-style intellectual property reuse in system-on-chip design is facilitated by the use of an on-chip bus architecture. Component integration and verification in such systems is a cumbersome and time consuming process largely concerned with interfacing issues. A synchronous, finite state ma...
| Main Authors: | , , |
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| Format: | Journal article |
| Published: |
2005
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