Automated pipeline design
The interlock and forwarding logic is considered the tricky part of fully-featured piplined microprocessor and especially debugging these parts delays the hardware design process considerably. It is therefore desirable to automate the design of both interlock and forwarding logic. The hardware desig...
| Main Authors: | , |
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| Format: | Conference item |
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ACM
2001
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| _version_ | 1826261296405807104 |
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| author | Kroening, D Paul, W |
| author_facet | Kroening, D Paul, W |
| author_sort | Kroening, D |
| collection | OXFORD |
| description | The interlock and forwarding logic is considered the tricky part of fully-featured piplined microprocessor and especially debugging these parts delays the hardware design process considerably. It is therefore desirable to automate the design of both interlock and forwarding logic. The hardware design engineer begins with a sequential implementation without any interlock and forwarding logic. A tool then adds the forwarding and interlock logic required for pipelining. This paper describes the algorithm for such a tool and the correctness is formally verified. We use a standard DLX RISC processor as an example. |
| first_indexed | 2024-03-06T19:19:13Z |
| format | Conference item |
| id | oxford-uuid:1979c692-dc60-45b7-b41f-a1b7fdced398 |
| institution | University of Oxford |
| last_indexed | 2024-03-06T19:19:13Z |
| publishDate | 2001 |
| publisher | ACM |
| record_format | dspace |
| spelling | oxford-uuid:1979c692-dc60-45b7-b41f-a1b7fdced3982022-03-26T10:49:15ZAutomated pipeline designConference itemhttp://purl.org/coar/resource_type/c_5794uuid:1979c692-dc60-45b7-b41f-a1b7fdced398Symplectic Elements at OxfordACM2001Kroening, DPaul, WThe interlock and forwarding logic is considered the tricky part of fully-featured piplined microprocessor and especially debugging these parts delays the hardware design process considerably. It is therefore desirable to automate the design of both interlock and forwarding logic. The hardware design engineer begins with a sequential implementation without any interlock and forwarding logic. A tool then adds the forwarding and interlock logic required for pipelining. This paper describes the algorithm for such a tool and the correctness is formally verified. We use a standard DLX RISC processor as an example. |
| spellingShingle | Kroening, D Paul, W Automated pipeline design |
| title | Automated pipeline design |
| title_full | Automated pipeline design |
| title_fullStr | Automated pipeline design |
| title_full_unstemmed | Automated pipeline design |
| title_short | Automated pipeline design |
| title_sort | automated pipeline design |
| work_keys_str_mv | AT kroeningd automatedpipelinedesign AT paulw automatedpipelinedesign |