Correctness of a Fault−Tolerant Real−Time Scheduler and its Hardware Implementation
We formalize the correctness of a fault-tolerant scheduler in a time-triggered architecture. Where previous research elaborated on real-time protocol correctness, we extend this work to gate-level hardware. This requires a sophisticated analysis of analog bit-level synchronization and transmission....
Main Authors: | Alkassar, E, Böhm, P, Knapp, S |
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Format: | Conference item |
Published: |
IEEE
2008
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