Area optimisation for field-programmable gate arrays in SystemC hardware compilation
This paper discusses a pair of synthesis algorithms that optimise a SystemC design to minimise area when targeting FPGAs. Each can significantly improve the synthesis of a high-level language construct, thus allowing a designer to concentrate more on an algorithm description and less on hardware-spe...
| Main Authors: | , , |
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| Format: | Journal article |
| Language: | English |
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Hindawi Publishing Corporation
2008
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| Subjects: |
| _version_ | 1797061944186765312 |
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| author | Ditmar, J McKeever, S Wilson, A |
| author_facet | Ditmar, J McKeever, S Wilson, A |
| author_sort | Ditmar, J |
| collection | OXFORD |
| description | This paper discusses a pair of synthesis algorithms that optimise a SystemC design to minimise area when targeting FPGAs. Each can significantly improve the synthesis of a high-level language construct, thus allowing a designer to concentrate more on an algorithm description and less on hardware-specific implementation details. The first algorithm is a source-level transformation implementing function exlining - where a separate block of hardware implements a function and is shared between multiple calls to the function. The second is a novel algorithm for mapping arrays to memories which involves assigning array accesses to memory ports such that no port is ever accessed more than once in a clock cycle. This algorithm assigns accesses to read/write only ports and read-write ports concurrently, solving the assignment problem more efficiently for a wider range of memories compared to existing methods. Both optimisations operate on a high-level program representation and have been implemented in a commercial SystemC compiler. Experiments show that in suitable circumstances these techniques result in significant reductions in logic utilisation for FPGAs. |
| first_indexed | 2024-03-06T20:38:26Z |
| format | Journal article |
| id | oxford-uuid:3369e82a-b73e-45b7-a981-c6102d9f0345 |
| institution | University of Oxford |
| language | English |
| last_indexed | 2024-03-06T20:38:26Z |
| publishDate | 2008 |
| publisher | Hindawi Publishing Corporation |
| record_format | dspace |
| spelling | oxford-uuid:3369e82a-b73e-45b7-a981-c6102d9f03452022-03-26T13:20:08ZArea optimisation for field-programmable gate arrays in SystemC hardware compilationJournal articlehttp://purl.org/coar/resource_type/c_dcae04bcuuid:3369e82a-b73e-45b7-a981-c6102d9f0345ComputingEnglishOxford University Research Archive - ValetHindawi Publishing Corporation2008Ditmar, JMcKeever, SWilson, AThis paper discusses a pair of synthesis algorithms that optimise a SystemC design to minimise area when targeting FPGAs. Each can significantly improve the synthesis of a high-level language construct, thus allowing a designer to concentrate more on an algorithm description and less on hardware-specific implementation details. The first algorithm is a source-level transformation implementing function exlining - where a separate block of hardware implements a function and is shared between multiple calls to the function. The second is a novel algorithm for mapping arrays to memories which involves assigning array accesses to memory ports such that no port is ever accessed more than once in a clock cycle. This algorithm assigns accesses to read/write only ports and read-write ports concurrently, solving the assignment problem more efficiently for a wider range of memories compared to existing methods. Both optimisations operate on a high-level program representation and have been implemented in a commercial SystemC compiler. Experiments show that in suitable circumstances these techniques result in significant reductions in logic utilisation for FPGAs. |
| spellingShingle | Computing Ditmar, J McKeever, S Wilson, A Area optimisation for field-programmable gate arrays in SystemC hardware compilation |
| title | Area optimisation for field-programmable gate arrays in SystemC hardware compilation |
| title_full | Area optimisation for field-programmable gate arrays in SystemC hardware compilation |
| title_fullStr | Area optimisation for field-programmable gate arrays in SystemC hardware compilation |
| title_full_unstemmed | Area optimisation for field-programmable gate arrays in SystemC hardware compilation |
| title_short | Area optimisation for field-programmable gate arrays in SystemC hardware compilation |
| title_sort | area optimisation for field programmable gate arrays in systemc hardware compilation |
| topic | Computing |
| work_keys_str_mv | AT ditmarj areaoptimisationforfieldprogrammablegatearraysinsystemchardwarecompilation AT mckeevers areaoptimisationforfieldprogrammablegatearraysinsystemchardwarecompilation AT wilsona areaoptimisationforfieldprogrammablegatearraysinsystemchardwarecompilation |