Area optimisation for field-programmable gate arrays in SystemC hardware compilation
This paper discusses a pair of synthesis algorithms that optimise a SystemC design to minimise area when targeting FPGAs. Each can significantly improve the synthesis of a high-level language construct, thus allowing a designer to concentrate more on an algorithm description and less on hardware-spe...
| Những tác giả chính: | , , |
|---|---|
| Định dạng: | Journal article |
| Ngôn ngữ: | English |
| Được phát hành: |
Hindawi Publishing Corporation
2008
|
| Những chủ đề: |
Search Result 1
Area Optimisation for Field−Programmable Gate Arrays in SystemC Hardware Compilation
Được phát hành 2008
Journal article