Area optimisation for field-programmable gate arrays in SystemC hardware compilation
This paper discusses a pair of synthesis algorithms that optimise a SystemC design to minimise area when targeting FPGAs. Each can significantly improve the synthesis of a high-level language construct, thus allowing a designer to concentrate more on an algorithm description and less on hardware-spe...
| Hauptverfasser: | , , |
|---|---|
| Format: | Journal article |
| Sprache: | English |
| Veröffentlicht: |
Hindawi Publishing Corporation
2008
|
| Schlagworte: |