| Ամփոփում: | A systematic investigation has been undertaken, in which thin polymer buffer layers with different ester content have been spin-coated onto a flash-evaporated, cross-linked diacrylate gate-insulator to form bottom-gate, top-contact organic thin-film transistors. The highest device mobilities, ∼0.65 cm<sup>2</sup>/V s and ∼1.00 cm<sup>2</sup>/V s for pentacene and dinaphtho[2,3-b:2′,3′-f]-thieno[3,2-b]thiophene (DNTT), respectively, were only observed for a combination of large-grain (∼1–2 <em>μ</em>m) semiconductor morphology coupled with a non-polar dielectric surface. No correlation was found between semiconductor grain size and dielectric surface chemistry. The threshold voltage of pentacene devices shifted from −10 V to −25 V with decreasing surface ester content, but remained close to 0 V for DNTT.
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