VLSI implementation of a fully-pipelined K-Best MIMO detector with successive interference cancellation
Multiple-input multiple-output (MIMO) technology is envisaged to play an important role in future wireless communications. To this end, novel algorithms and architectures are required to implement high-throughput MIMO communications at low power consumption. In this paper, we present the hardware im...
| Main Authors: | , , , |
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| Format: | Journal article |
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Springer
2019
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| _version_ | 1797066196568244224 |
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| author | Bello, I Halak, B El-Hajjar, M Zwolinski, M |
| author_facet | Bello, I Halak, B El-Hajjar, M Zwolinski, M |
| author_sort | Bello, I |
| collection | OXFORD |
| description | Multiple-input multiple-output (MIMO) technology is envisaged to play an important role in future wireless communications. To this end, novel algorithms and architectures are required to implement high-throughput MIMO communications at low power consumption. In this paper, we present the hardware implementation of a modified K-best algorithm combining conventional K-best detection and low-complexity successive interference cancellation at different levels of the tree search. The detector is implemented using a fully-pipelined architecture, which detects one symbol vector per clock cycle. To reduce the power consumption of the entire receiver unit, costly symbol-rate operations such as multiplication are eliminated both within and outside the detector without any impact on the performance. The hardware implementation of the modified K-best algorithm achieves area and power reductions of 16% and 38%, respectively, compared with the conventional K-best algorithm implementation, while incurring a signal-to-noise ratio penalty of 0.3 dB at the target bit error rate. Post-synthesis analysis shows that the detector achieves a throughput of 3.29 Gbps at a clock frequency of 137 MHz with a power consumption of 357 mW using a 65-nm CMOS process, which compares favourably with the state-of-the-art implementations in the literature. |
| first_indexed | 2024-03-06T21:38:58Z |
| format | Journal article |
| id | oxford-uuid:473ead41-08e2-4c19-9c74-b8be3b76246c |
| institution | University of Oxford |
| last_indexed | 2024-03-06T21:38:58Z |
| publishDate | 2019 |
| publisher | Springer |
| record_format | dspace |
| spelling | oxford-uuid:473ead41-08e2-4c19-9c74-b8be3b76246c2022-03-26T15:18:57ZVLSI implementation of a fully-pipelined K-Best MIMO detector with successive interference cancellationJournal articlehttp://purl.org/coar/resource_type/c_dcae04bcuuid:473ead41-08e2-4c19-9c74-b8be3b76246cSymplectic Elements at OxfordSpringer2019Bello, IHalak, BEl-Hajjar, MZwolinski, MMultiple-input multiple-output (MIMO) technology is envisaged to play an important role in future wireless communications. To this end, novel algorithms and architectures are required to implement high-throughput MIMO communications at low power consumption. In this paper, we present the hardware implementation of a modified K-best algorithm combining conventional K-best detection and low-complexity successive interference cancellation at different levels of the tree search. The detector is implemented using a fully-pipelined architecture, which detects one symbol vector per clock cycle. To reduce the power consumption of the entire receiver unit, costly symbol-rate operations such as multiplication are eliminated both within and outside the detector without any impact on the performance. The hardware implementation of the modified K-best algorithm achieves area and power reductions of 16% and 38%, respectively, compared with the conventional K-best algorithm implementation, while incurring a signal-to-noise ratio penalty of 0.3 dB at the target bit error rate. Post-synthesis analysis shows that the detector achieves a throughput of 3.29 Gbps at a clock frequency of 137 MHz with a power consumption of 357 mW using a 65-nm CMOS process, which compares favourably with the state-of-the-art implementations in the literature. |
| spellingShingle | Bello, I Halak, B El-Hajjar, M Zwolinski, M VLSI implementation of a fully-pipelined K-Best MIMO detector with successive interference cancellation |
| title | VLSI implementation of a fully-pipelined K-Best MIMO detector with successive interference cancellation |
| title_full | VLSI implementation of a fully-pipelined K-Best MIMO detector with successive interference cancellation |
| title_fullStr | VLSI implementation of a fully-pipelined K-Best MIMO detector with successive interference cancellation |
| title_full_unstemmed | VLSI implementation of a fully-pipelined K-Best MIMO detector with successive interference cancellation |
| title_short | VLSI implementation of a fully-pipelined K-Best MIMO detector with successive interference cancellation |
| title_sort | vlsi implementation of a fully pipelined k best mimo detector with successive interference cancellation |
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