An improved parallel archutecture for MPEG-4 motion estimation in 3G mobile applications
A high-parallel VLSI core architecture for MPEG-4 motion estimation is proposed in this paper. It possesses the characteristics of low memory bandwidth and low clock rate requirements, thus primarily aiming at 3G mobile applications. Based on a one-dimensional tree architecture, the architecture emp...
| Main Authors: | , , , |
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| Format: | Conference item |
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2003
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| _version_ | 1826270333119758336 |
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| author | Xu, D Gao, R Batatia, H IEEE IEEE IEEE |
| author_facet | Xu, D Gao, R Batatia, H IEEE IEEE IEEE |
| author_sort | Xu, D |
| collection | OXFORD |
| description | A high-parallel VLSI core architecture for MPEG-4 motion estimation is proposed in this paper. It possesses the characteristics of low memory bandwidth and low clock rate requirements, thus primarily aiming at 3G mobile applications. Based on a one-dimensional tree architecture, the architecture employs the dual-register/buffer technique to reduce the preload and alignment cycles. As an example, full-search block matching algorithm has been mapped onto this architecture using a 16-PE array that has the ability to calculate the motion vectors of QCIF video sequences in real time at 1 MHz clock rate and using 15.5 Mbytes/s memory bandwidth. |
| first_indexed | 2024-03-06T21:39:11Z |
| format | Conference item |
| id | oxford-uuid:474ee4e8-b0c1-49e5-abb3-3573a53eca7a |
| institution | University of Oxford |
| last_indexed | 2024-03-06T21:39:11Z |
| publishDate | 2003 |
| record_format | dspace |
| spelling | oxford-uuid:474ee4e8-b0c1-49e5-abb3-3573a53eca7a2022-03-26T15:19:25ZAn improved parallel archutecture for MPEG-4 motion estimation in 3G mobile applicationsConference itemhttp://purl.org/coar/resource_type/c_5794uuid:474ee4e8-b0c1-49e5-abb3-3573a53eca7aSymplectic Elements at Oxford2003Xu, DGao, RBatatia, HIEEEIEEEIEEEA high-parallel VLSI core architecture for MPEG-4 motion estimation is proposed in this paper. It possesses the characteristics of low memory bandwidth and low clock rate requirements, thus primarily aiming at 3G mobile applications. Based on a one-dimensional tree architecture, the architecture employs the dual-register/buffer technique to reduce the preload and alignment cycles. As an example, full-search block matching algorithm has been mapped onto this architecture using a 16-PE array that has the ability to calculate the motion vectors of QCIF video sequences in real time at 1 MHz clock rate and using 15.5 Mbytes/s memory bandwidth. |
| spellingShingle | Xu, D Gao, R Batatia, H IEEE IEEE IEEE An improved parallel archutecture for MPEG-4 motion estimation in 3G mobile applications |
| title | An improved parallel archutecture for MPEG-4 motion estimation in 3G mobile applications |
| title_full | An improved parallel archutecture for MPEG-4 motion estimation in 3G mobile applications |
| title_fullStr | An improved parallel archutecture for MPEG-4 motion estimation in 3G mobile applications |
| title_full_unstemmed | An improved parallel archutecture for MPEG-4 motion estimation in 3G mobile applications |
| title_short | An improved parallel archutecture for MPEG-4 motion estimation in 3G mobile applications |
| title_sort | improved parallel archutecture for mpeg 4 motion estimation in 3g mobile applications |
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