Design of a prototype frontend and bias generator for a new readout chip for LHCb
This paper presents the design and simulation results of components for a new LHCb readout chip for the silicon vertex detector, the inner tracking system, the pile-up veto trigger and the RICH. It is planned to use the same readout chip for these subdetectors. However, different versions of the ana...
| Hoofdauteurs: | , , , , , , , , |
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| Formaat: | Conference item |
| Gepubliceerd in: |
1999
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| _version_ | 1826273057355857920 |
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| author | van Bakel, N van den Brand, J Knopfle, K Schmelling, M Sexauer, E Feuerstack-Raible, M Harnew, N Smale, N CERN CERN |
| author_facet | van Bakel, N van den Brand, J Knopfle, K Schmelling, M Sexauer, E Feuerstack-Raible, M Harnew, N Smale, N CERN CERN |
| author_sort | van Bakel, N |
| collection | OXFORD |
| description | This paper presents the design and simulation results of components for a new LHCb readout chip for the silicon vertex detector, the inner tracking system, the pile-up veto trigger and the RICH. It is planned to use the same readout chip for these subdetectors. However, different versions of the analog input stages might be developed depending on the choice of the detector type.In section 1, the specification of the new readout chip named Beetle with respect to the different subdetector systems is described. Sections 2 and 3 describe the design and the simulation results of two test chips. The first chip contains different types of frontends for the vertex detector and the second chip bias generators. Section 4 gives a brief overview on the future plans for the development towards a readout chip for LHCb. |
| first_indexed | 2024-03-06T22:22:20Z |
| format | Conference item |
| id | oxford-uuid:55795290-ab45-461f-bf6e-721a46f57bc8 |
| institution | University of Oxford |
| last_indexed | 2024-03-06T22:22:20Z |
| publishDate | 1999 |
| record_format | dspace |
| spelling | oxford-uuid:55795290-ab45-461f-bf6e-721a46f57bc82022-03-26T16:44:18ZDesign of a prototype frontend and bias generator for a new readout chip for LHCbConference itemhttp://purl.org/coar/resource_type/c_5794uuid:55795290-ab45-461f-bf6e-721a46f57bc8Symplectic Elements at Oxford1999van Bakel, Nvan den Brand, JKnopfle, KSchmelling, MSexauer, EFeuerstack-Raible, MHarnew, NSmale, NCERNCERNThis paper presents the design and simulation results of components for a new LHCb readout chip for the silicon vertex detector, the inner tracking system, the pile-up veto trigger and the RICH. It is planned to use the same readout chip for these subdetectors. However, different versions of the analog input stages might be developed depending on the choice of the detector type.In section 1, the specification of the new readout chip named Beetle with respect to the different subdetector systems is described. Sections 2 and 3 describe the design and the simulation results of two test chips. The first chip contains different types of frontends for the vertex detector and the second chip bias generators. Section 4 gives a brief overview on the future plans for the development towards a readout chip for LHCb. |
| spellingShingle | van Bakel, N van den Brand, J Knopfle, K Schmelling, M Sexauer, E Feuerstack-Raible, M Harnew, N Smale, N CERN CERN Design of a prototype frontend and bias generator for a new readout chip for LHCb |
| title | Design of a prototype frontend and bias generator for a new readout chip for LHCb |
| title_full | Design of a prototype frontend and bias generator for a new readout chip for LHCb |
| title_fullStr | Design of a prototype frontend and bias generator for a new readout chip for LHCb |
| title_full_unstemmed | Design of a prototype frontend and bias generator for a new readout chip for LHCb |
| title_short | Design of a prototype frontend and bias generator for a new readout chip for LHCb |
| title_sort | design of a prototype frontend and bias generator for a new readout chip for lhcb |
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