Design of a prototype frontend and bias generator for a new readout chip for LHCb

Design of a prototype frontend and bias generator for a new readout chip for LHCb

This paper presents the design and simulation results of components for a new LHCb readout chip for the silicon vertex detector, the inner tracking system, the pile-up veto trigger and the RICH. It is planned to use the same readout chip for these subdetectors. However, different versions of the ana...

Disgrifiad llawn

Manylion Llyfryddiaeth
Prif Awduron:	van Bakel, N, van den Brand, J, Knopfle, K, Schmelling, M, Sexauer, E, Feuerstack-Raible, M, Harnew, N, Smale, N, CERN
Fformat:	Conference item
Cyhoeddwyd:	1999

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