Design of a prototype frontend and bias generator for a new readout chip for LHCb
This paper presents the design and simulation results of components for a new LHCb readout chip for the silicon vertex detector, the inner tracking system, the pile-up veto trigger and the RICH. It is planned to use the same readout chip for these subdetectors. However, different versions of the ana...
| Հիմնական հեղինակներ: | , , , , , , , , |
|---|---|
| Ձևաչափ: | Conference item |
| Հրապարակվել է: |
1999
|