Design and Verification of On−Chip Communication Protocols

Design and Verification of On−Chip Communication Protocols

Show other versions (2)

Manylion Llyfryddiaeth
Prif Awduron:	Böhm, P, Melham, T
Fformat:	Conference item
Cyhoeddwyd:	ETAPS 2008 2008

Eitemau Tebyg

Design and Verification of On−Chip Communication Protocols
gan: Böhm, P, et al.
Cyhoeddwyd: (2015)

Design and Verification of On−Chip Communication Protocols
gan: Böhm, P, et al.
Cyhoeddwyd: (2015)

A Refinement Approach to Design and Verification of On−Chip Communication Protocols
gan: Böhm, P, et al.
Cyhoeddwyd: (2008)

A Refinement Approach to Design and Verification of On−Chip Communication Protocols
gan: Böhm, P, et al.
Cyhoeddwyd: (2008)

A Refinement Approach to Design and Verification of On-Chip Communication Protocols
gan: Boehm, P, et al.
Cyhoeddwyd: (2008)

A Framework for Incremental Modelling and Verification of On−Chip Protocols
gan: Böhm, P
Cyhoeddwyd: (2010)

Abstraction Mechanisms for Hardware Verification
gan: Melham, T
Cyhoeddwyd: (1990)

Abstraction Mechanisms for Hardware Verification
gan: Melham, T
Cyhoeddwyd: (1988)

Abstraction Mechanisms for Hardware Verification
gan: Melham, T
Cyhoeddwyd: (1987)

A Formalised Framework for Incremental Modelling of On−Chip Communication
gan: Böhm, P
Cyhoeddwyd: (2010)

Higher Order Logic and Hardware Verification
gan: Melham, T
Cyhoeddwyd: (1993)

Practical Formal Verification in Microprocessor Design
gan: Jones, R, et al.
Cyhoeddwyd: (2015)

Abstract: Experience with Practical Formal Verification at an Industrial Scale
gan: Melham, T
Cyhoeddwyd: (2003)

Relational STE and Theorem Proving for Formal Verification of Industrial Circuit Designs
gan: O'Leary, J, et al.
Cyhoeddwyd: (2013)

Relational STE and theorem proving for formal verification of industrial circuit designs
gan: O'Leary, J, et al.
Cyhoeddwyd: (2013)

Formalizing Abstraction Mechanisms for Hardware Verification in Higher Order Logic
gan: Melham, T
Cyhoeddwyd: (1989)

Contextualizing formal verification for systems security engineering
gan: Shaked, A, et al.
Cyhoeddwyd: (2024)

An AMBA−ARM7 Formal Verification Platform
gan: Susanto, K, et al.
Cyhoeddwyd: (2003)

MODELLING AND VERIFICATION OF KITSAT PACKET COMMUNICATION PROTOCOLS
gan: Young-Ro Lee, et al.
Cyhoeddwyd: (1996-06-01)

Hardware/Software Implementation of a Chip-to-Chip Communication Protocol Based on SPDM
gan: Kais Belwafi, et al.
Cyhoeddwyd: (2024-01-01)

Design and post-silicon verification of polymorphic PCIE bridge expansion chip
gan: Deng Jiawei, et al.
Cyhoeddwyd: (2023-02-01)

Hardware verification using software analyzers
gan: Mukherjee, R, et al.
Cyhoeddwyd: (2015)

Hardware Verification by Formal Proof
gan: Birtwistle, G, et al.
Cyhoeddwyd: (1988)

Hardware Verification by Formal Proof
gan: Birtwistle, G, et al.
Cyhoeddwyd: (1988)

Hardware Verification using Higher−Order Logic
gan: Camilleri, A, et al.
Cyhoeddwyd: (1986)

Hardware Verification using Higher−Order Logic
gan: Camilleri, A, et al.
Cyhoeddwyd: (1987)

A formal CHERI-C semantics for verification
gan: Park, SH, et al.
Cyhoeddwyd: (2023)

Design and implementation of adaptive and synchronous test function of chip sample verification platform
gan: Xu Jinglin, et al.
Cyhoeddwyd: (2023-02-01)

Unbounded Safety Verification for Hardware Using Software Analyzers
gan: Mukherjee, R, et al.
Cyhoeddwyd: (2015)

End-to-end formal verification of a RISC-V processor extended with capability pointers
gan: Gao, D, et al.
Cyhoeddwyd: (2021)

Method for reducing the complexity of clock domain crossing design and its verification in system-on-chips
gan: Dan LIU, et al.
Cyhoeddwyd: (2012-11-01)

Method for reducing the complexity of clock domain crossing design and its verification in system-on-chips
gan: Dan LIU, et al.
Cyhoeddwyd: (2012-11-01)

Verification methods for complex-functional blocks in CAD for chips deep submicron design standards
gan: Zolnikov Vladimir, et al.
Cyhoeddwyd: (2023-01-01)

Design and verification of adaptive cache coherence protocols
gan: Shen, Xiaowei, 1966-
Cyhoeddwyd: (2014)

Effective verification for low-level software with competing interrupts
gan: Liang, L, et al.
Cyhoeddwyd: (2017)

Verification of an artificial intelligence vision chip design for edge computing based on hardware simulation system
gan: Xuanzhe XU, et al.
Cyhoeddwyd: (2022-03-01)

Verification of an artificial intelligence vision chip design for edge computing based on hardware simulation system
gan: Xuanzhe XU, et al.
Cyhoeddwyd: (2022-03-01)

Lifting CDCL to template-based abstract domains for program verification
gan: Mukherjee, R, et al.
Cyhoeddwyd: (2017)

Verification of communication protocols in web services : model-checking service compositions /
gan: 464078 Tari, Zahir, et al.
Cyhoeddwyd: (2014)

RFID security : techniques, protocols and system-on-chip design /
gan: Kitsos, Paris, 1952-, et al.
Cyhoeddwyd: (2008)