Design and Verification of On−Chip Communication Protocols

Design and Verification of On−Chip Communication Protocols

Taispeáin leaganacha eile (2)

Sonraí bibleagrafaíochta
Príomhchruthaitheoirí:	Böhm, P, Melham, T
Formáid:	Conference item
Foilsithe / Cruthaithe:	ETAPS 2008 2008

Míreanna comhchosúla

Design and Verification of On−Chip Communication Protocols
de réir: Böhm, P, et al.
Foilsithe / Cruthaithe: (2015)

Design and Verification of On−Chip Communication Protocols
de réir: Böhm, P, et al.
Foilsithe / Cruthaithe: (2015)

A Refinement Approach to Design and Verification of On−Chip Communication Protocols
de réir: Böhm, P, et al.
Foilsithe / Cruthaithe: (2008)

A Refinement Approach to Design and Verification of On−Chip Communication Protocols
de réir: Böhm, P, et al.
Foilsithe / Cruthaithe: (2008)

A Refinement Approach to Design and Verification of On-Chip Communication Protocols
de réir: Boehm, P, et al.
Foilsithe / Cruthaithe: (2008)

A Framework for Incremental Modelling and Verification of On−Chip Protocols
de réir: Böhm, P
Foilsithe / Cruthaithe: (2010)

Abstraction Mechanisms for Hardware Verification
de réir: Melham, T
Foilsithe / Cruthaithe: (1990)

Abstraction Mechanisms for Hardware Verification
de réir: Melham, T
Foilsithe / Cruthaithe: (1988)

Abstraction Mechanisms for Hardware Verification
de réir: Melham, T
Foilsithe / Cruthaithe: (1987)

A Formalised Framework for Incremental Modelling of On−Chip Communication
de réir: Böhm, P
Foilsithe / Cruthaithe: (2010)

Higher Order Logic and Hardware Verification
de réir: Melham, T
Foilsithe / Cruthaithe: (1993)

Practical Formal Verification in Microprocessor Design
de réir: Jones, R, et al.
Foilsithe / Cruthaithe: (2015)

Abstract: Experience with Practical Formal Verification at an Industrial Scale
de réir: Melham, T
Foilsithe / Cruthaithe: (2003)

Relational STE and Theorem Proving for Formal Verification of Industrial Circuit Designs
de réir: O'Leary, J, et al.
Foilsithe / Cruthaithe: (2013)

Relational STE and theorem proving for formal verification of industrial circuit designs
de réir: O'Leary, J, et al.
Foilsithe / Cruthaithe: (2013)

Formalizing Abstraction Mechanisms for Hardware Verification in Higher Order Logic
de réir: Melham, T
Foilsithe / Cruthaithe: (1989)

Contextualizing formal verification for systems security engineering
de réir: Shaked, A, et al.
Foilsithe / Cruthaithe: (2024)

An AMBA−ARM7 Formal Verification Platform
de réir: Susanto, K, et al.
Foilsithe / Cruthaithe: (2003)

MODELLING AND VERIFICATION OF KITSAT PACKET COMMUNICATION PROTOCOLS
de réir: Young-Ro Lee, et al.
Foilsithe / Cruthaithe: (1996-06-01)

Hardware/Software Implementation of a Chip-to-Chip Communication Protocol Based on SPDM
de réir: Kais Belwafi, et al.
Foilsithe / Cruthaithe: (2024-01-01)

Design and post-silicon verification of polymorphic PCIE bridge expansion chip
de réir: Deng Jiawei, et al.
Foilsithe / Cruthaithe: (2023-02-01)

Hardware verification using software analyzers
de réir: Mukherjee, R, et al.
Foilsithe / Cruthaithe: (2015)

Hardware Verification by Formal Proof
de réir: Birtwistle, G, et al.
Foilsithe / Cruthaithe: (1988)

Hardware Verification by Formal Proof
de réir: Birtwistle, G, et al.
Foilsithe / Cruthaithe: (1988)

Hardware Verification using Higher−Order Logic
de réir: Camilleri, A, et al.
Foilsithe / Cruthaithe: (1986)

Hardware Verification using Higher−Order Logic
de réir: Camilleri, A, et al.
Foilsithe / Cruthaithe: (1987)

A formal CHERI-C semantics for verification
de réir: Park, SH, et al.
Foilsithe / Cruthaithe: (2023)

Design and implementation of adaptive and synchronous test function of chip sample verification platform
de réir: Xu Jinglin, et al.
Foilsithe / Cruthaithe: (2023-02-01)

Unbounded Safety Verification for Hardware Using Software Analyzers
de réir: Mukherjee, R, et al.
Foilsithe / Cruthaithe: (2015)

End-to-end formal verification of a RISC-V processor extended with capability pointers
de réir: Gao, D, et al.
Foilsithe / Cruthaithe: (2021)

Method for reducing the complexity of clock domain crossing design and its verification in system-on-chips
de réir: Dan LIU, et al.
Foilsithe / Cruthaithe: (2012-11-01)

Method for reducing the complexity of clock domain crossing design and its verification in system-on-chips
de réir: Dan LIU, et al.
Foilsithe / Cruthaithe: (2012-11-01)

Verification methods for complex-functional blocks in CAD for chips deep submicron design standards
de réir: Zolnikov Vladimir, et al.
Foilsithe / Cruthaithe: (2023-01-01)

Design and verification of adaptive cache coherence protocols
de réir: Shen, Xiaowei, 1966-
Foilsithe / Cruthaithe: (2014)

Effective verification for low-level software with competing interrupts
de réir: Liang, L, et al.
Foilsithe / Cruthaithe: (2017)

Verification of an artificial intelligence vision chip design for edge computing based on hardware simulation system
de réir: Xuanzhe XU, et al.
Foilsithe / Cruthaithe: (2022-03-01)

Verification of an artificial intelligence vision chip design for edge computing based on hardware simulation system
de réir: Xuanzhe XU, et al.
Foilsithe / Cruthaithe: (2022-03-01)

Lifting CDCL to template-based abstract domains for program verification
de réir: Mukherjee, R, et al.
Foilsithe / Cruthaithe: (2017)

Verification of communication protocols in web services : model-checking service compositions /
de réir: 464078 Tari, Zahir, et al.
Foilsithe / Cruthaithe: (2014)

RFID security : techniques, protocols and system-on-chip design /
de réir: Kitsos, Paris, 1952-, et al.
Foilsithe / Cruthaithe: (2008)