Unbounded Safety Verification for Hardware Using Software Analyzers
Demand for scalable hardware verification is ever increasing. We propose an unbounded safety verification framework for hardware, at the heart of which is a software verifier. To this end, we synthesize Verilog at register transfer level into a software-netlist, represented as a word-level ANSI-C pr...
| Hauptverfasser: | , , , |
|---|---|
| Format: | Conference item |
| Veröffentlicht: |
European Design and Automation Association
2015
|