APA-Zitierstil (7. Ausg.)

Jain, H., Sharygina, N., Kroening, D., Clarke, E., & Jr, W. (2005). Word level predicate abstraction and refinement for verifying RTL verilog. Association for Computing Machinery.

Chicago-Zitierstil (17. Ausg.)

Jain, H., N. Sharygina, D. Kroening, E. Clarke, und W. Jr. Word Level Predicate Abstraction and Refinement for Verifying RTL Verilog. Association for Computing Machinery, 2005.

MLA-Zitierstil (9. Ausg.)

Jain, H., et al. Word Level Predicate Abstraction and Refinement for Verifying RTL Verilog. Association for Computing Machinery, 2005.