Cita APA (7a ed.)

Jain, H., Sharygina, N., Kroening, D., Clarke, E., & Jr, W. (2005). Word level predicate abstraction and refinement for verifying RTL verilog. Association for Computing Machinery.

Cita Chicago Style (17a ed.)

Jain, H., N. Sharygina, D. Kroening, E. Clarke, y W. Jr. Word Level Predicate Abstraction and Refinement for Verifying RTL Verilog. Association for Computing Machinery, 2005.

Cita MLA (9a ed.)

Jain, H., et al. Word Level Predicate Abstraction and Refinement for Verifying RTL Verilog. Association for Computing Machinery, 2005.