Jain, H., Sharygina, N., Kroening, D., Clarke, E., & Jr, W. (2005). Word level predicate abstraction and refinement for verifying RTL verilog. Association for Computing Machinery.
Chicagoスタイル(17版)引用形式Jain, H., N. Sharygina, D. Kroening, E. Clarke, , W. Jr. Word Level Predicate Abstraction and Refinement for Verifying RTL Verilog. Association for Computing Machinery, 2005.
MLA(9版)引用形式Jain, H., et al. Word Level Predicate Abstraction and Refinement for Verifying RTL Verilog. Association for Computing Machinery, 2005.
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