APA引文

Jain, H., Sharygina, N., Kroening, D., Clarke, E., & Jr, W. (2005). Word level predicate abstraction and refinement for verifying RTL verilog. Association for Computing Machinery.

Chicago Style (17th ed.) Citation

Jain, H., N. Sharygina, D. Kroening, E. Clarke, and W. Jr. Word Level Predicate Abstraction and Refinement for Verifying RTL Verilog. Association for Computing Machinery, 2005.

MLA引文

Jain, H., et al. Word Level Predicate Abstraction and Refinement for Verifying RTL Verilog. Association for Computing Machinery, 2005.