Word level predicate abstraction and refinement for verifying RTL verilog

Word level predicate abstraction and refinement for verifying RTL verilog

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Model checking techniques applied to large industrial circuits suffer from the state space explosion problem. A major technique to address this problem is abstraction. The most commonly used abstraction technique for hardware verification is localization reduction, which removes latches that are not...

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Bibliografiske detaljer
Main Authors:	Jain, H, Sharygina, N, Kroening, D, Clarke, E
Andre forfattere:	Jr, W
Format:	Conference item
Udgivet:	Association for Computing Machinery 2005

Lignende værker

Word Level Predicate Abstraction and Refinement for Verifying RTL Verilog
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Udgivet: (2005)

Word Level Predicate Abstraction and Refinement for Verifying RTL Verilog
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Word-Level Predicate-Abstraction and Refinement Techniques for Verifying RTL Verilog.
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Word-level predicate-abstraction and refinement rechniques for verifying RTL Verilog
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Predicate Abstraction of ANSI-C Programs Using SAT.
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Predicate Abstraction of ANSI-C Programs Using SAT
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Counterexamples with Loops for Predicate Abstraction
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Verification and Falsification of Programs with Loops Using Predicate Abstraction
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Verification and falsification of programs with loops using predicate abstraction.
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