Word level predicate abstraction and refinement for verifying RTL verilog

Model checking techniques applied to large industrial circuits suffer from the state space explosion problem. A major technique to address this problem is abstraction. The most commonly used abstraction technique for hardware verification is localization reduction, which removes latches that are not...

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গ্রন্থ-পঞ্জীর বিবরন
প্রধান লেখক:	Jain, H, Sharygina, N, Kroening, D, Clarke, E
অন্যান্য লেখক:	Jr, W
বিন্যাস:	Conference item
প্রকাশিত:	Association for Computing Machinery 2005

Word Level Predicate Abstraction and Refinement for Verifying RTL Verilog অনুযায়ী Jain, H, Kroening, D, Sharygina, N, Clarke, E

প্রকাশিত 2008

Journal article

Word Level Predicate Abstraction and Refinement for Verifying RTL Verilog অনুযায়ী Jain, H, Kroening, D, Sharygina, N, Clarke, E

প্রকাশিত 2005

Conference item

Word level predicate abstraction and refinement for verifying RTL verilog

Word Level Predicate Abstraction and Refinement for Verifying RTL Verilog অনুযায়ী Jain, H, Kroening, D, Sharygina, N, Clarke, E

Word Level Predicate Abstraction and Refinement for Verifying RTL Verilog অনুযায়ী Jain, H, Kroening, D, Sharygina, N, Clarke, E

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