Word level predicate abstraction and refinement for verifying RTL verilog

Model checking techniques applied to large industrial circuits suffer from the state space explosion problem. A major technique to address this problem is abstraction. The most commonly used abstraction technique for hardware verification is localization reduction, which removes latches that are not...

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Detaylı Bibliyografya
Asıl Yazarlar:	Jain, H, Sharygina, N, Kroening, D, Clarke, E
Diğer Yazarlar:	Jr, W
Materyal Türü:	Conference item
Baskı/Yayın Bilgisi:	Association for Computing Machinery 2005

Word Level Predicate Abstraction and Refinement for Verifying RTL Verilog Yazar: Jain, H, Kroening, D, Sharygina, N, Clarke, E

Baskı/Yayın Bilgisi 2008

Journal article

Word Level Predicate Abstraction and Refinement for Verifying RTL Verilog Yazar: Jain, H, Kroening, D, Sharygina, N, Clarke, E

Baskı/Yayın Bilgisi 2005

Conference item

Word level predicate abstraction and refinement for verifying RTL verilog

Word Level Predicate Abstraction and Refinement for Verifying RTL Verilog Yazar: Jain, H, Kroening, D, Sharygina, N, Clarke, E

Word Level Predicate Abstraction and Refinement for Verifying RTL Verilog Yazar: Jain, H, Kroening, D, Sharygina, N, Clarke, E

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