Word level predicate abstraction and refinement for verifying RTL verilog

Model checking techniques applied to large industrial circuits suffer from the state space explosion problem. A major technique to address this problem is abstraction. The most commonly used abstraction technique for hardware verification is localization reduction, which removes latches that are not...

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Hlavní autoři: Jain, H, Sharygina, N, Kroening, D, Clarke, E
Další autoři: Jr, W
Médium: Conference item
Vydáno: Association for Computing Machinery 2005