Word level predicate abstraction and refinement for verifying RTL verilog
Model checking techniques applied to large industrial circuits suffer from the state space explosion problem. A major technique to address this problem is abstraction. The most commonly used abstraction technique for hardware verification is localization reduction, which removes latches that are not...
Main Authors: | , , , |
---|---|
Outros autores: | |
Formato: | Conference item |
Publicado: |
Association for Computing Machinery
2005
|