Cita APA (7th ed.)

Jain, H., Kroening, D., Sharygina, N., & Clarke, E. (2007). VCEGAR: Verilog CounterExample Guided Abstraction Refinement. Springer.

Cita Chicago (17th ed.)

Jain, H., D. Kroening, N. Sharygina, i E. Clarke. VCEGAR: Verilog CounterExample Guided Abstraction Refinement. Springer, 2007.

Cita MLA (9th ed.)

Jain, H., et al. VCEGAR: Verilog CounterExample Guided Abstraction Refinement. Springer, 2007.