Dyfyniad APA

Jain, H., Kroening, D., Sharygina, N., & Clarke, E. (2007). VCEGAR: Verilog CounterExample Guided Abstraction Refinement. Springer.

Dyfyniad Arddull Chicago

Jain, H., D. Kroening, N. Sharygina, and E. Clarke. VCEGAR: Verilog CounterExample Guided Abstraction Refinement. Springer, 2007.

Dyfyniad MLA

Jain, H., et al. VCEGAR: Verilog CounterExample Guided Abstraction Refinement. Springer, 2007.

Rhybudd: Mae'n bosib nad yw'r dyfyniadau hyn bob amser yn 100% cywir.