Jain, H., Kroening, D., Sharygina, N., & Clarke, E. (2007). VCEGAR: Verilog CounterExample Guided Abstraction Refinement. Springer.
Chicago Style (17th ed.) CitationJain, H., D. Kroening, N. Sharygina, and E. Clarke. VCEGAR: Verilog CounterExample Guided Abstraction Refinement. Springer, 2007.
MLA (9th ed.) CitationJain, H., et al. VCEGAR: Verilog CounterExample Guided Abstraction Refinement. Springer, 2007.
Warning: These citations may not always be 100% accurate.