Jain, H., Kroening, D., Sharygina, N., & Clarke, E. (2007). VCEGAR: Verilog CounterExample Guided Abstraction Refinement. Springer.
Chicagoスタイル(17版)引用形式Jain, H., D. Kroening, N. Sharygina, , E. Clarke. VCEGAR: Verilog CounterExample Guided Abstraction Refinement. Springer, 2007.
MLA(9版)引用形式Jain, H., et al. VCEGAR: Verilog CounterExample Guided Abstraction Refinement. Springer, 2007.
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