VCEGAR: Verilog CounterExample Guided Abstraction Refinement
Principais autores: | Jain, H, Kroening, D, Sharygina, N, Clarke, E |
---|---|
Formato: | Conference item |
Publicado em: |
Springer
2007
|
Registros relacionados
-
Word Level Predicate Abstraction and Refinement for Verifying RTL Verilog
por: Jain, H, et al.
Publicado em: (2008) -
Word Level Predicate Abstraction and Refinement for Verifying RTL Verilog
por: Jain, H, et al.
Publicado em: (2005) -
Word level predicate abstraction and refinement for verifying RTL verilog
por: Jain, H, et al.
Publicado em: (2005) -
Word-Level Predicate-Abstraction and Refinement Techniques for Verifying RTL Verilog.
por: Jain, H, et al.
Publicado em: (2008) -
Word-level predicate-abstraction and refinement rechniques for verifying RTL Verilog
por: Jain, H, et al.
Publicado em: (2008)