VCEGAR: Verilog CounterExample Guided Abstraction Refinement

VCEGAR: Verilog CounterExample Guided Abstraction Refinement

Библиографические подробности
Главные авторы:	Jain, H, Kroening, D, Sharygina, N, Clarke, E
Формат:	Conference item
Опубликовано:	Springer 2007

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