Area Optimisation for Field−Programmable Gate Arrays in SystemC Hardware Compilation

This paper discusses a pair of synthesis algorithms that optimise a SystemC design to minimise area when targeting FPGAs. Each can significantly improve the synthesis of a high-level language construct, thus allowing a designer to concentrate more on an algorithm description and less on hardware-spe...

Повний опис

Бібліографічні деталі
Автори: Ditmar, J, McKeever, S, Wilson, A
Формат: Journal article
Опубліковано: 2008
_version_ 1826301064713863168
author Ditmar, J
McKeever, S
Wilson, A
author_facet Ditmar, J
McKeever, S
Wilson, A
author_sort Ditmar, J
collection OXFORD
description This paper discusses a pair of synthesis algorithms that optimise a SystemC design to minimise area when targeting FPGAs. Each can significantly improve the synthesis of a high-level language construct, thus allowing a designer to concentrate more on an algorithm description and less on hardware-specific implementation details. The first algorithm is a source-level transformation implementing function exlining—where a separate block of hardware implements a function and is shared between multiple calls to the function. The second is a novel algorithm for mapping arrays to memories which involves assigning array accesses to memory ports such that no port is ever accessed more than once in a clock cycle. This algorithm assigns accesses to read/write only ports and read-write ports concurrently, solving the assignment problem more efficiently for a wider range of memories compared to existing methods. Both optimisations operate on a high-level program representation and have been implemented in a commercial SystemC compiler. Experiments show that in suitable circumstances these techniques result in significant reductions in logic utilisation for FPGAs.
first_indexed 2024-03-07T05:26:42Z
format Journal article
id oxford-uuid:e0ced6e9-409f-45da-9c8c-5b37995e45a3
institution University of Oxford
last_indexed 2024-03-07T05:26:42Z
publishDate 2008
record_format dspace
spelling oxford-uuid:e0ced6e9-409f-45da-9c8c-5b37995e45a32022-03-27T09:50:01ZArea Optimisation for Field−Programmable Gate Arrays in SystemC Hardware CompilationJournal articlehttp://purl.org/coar/resource_type/c_dcae04bcuuid:e0ced6e9-409f-45da-9c8c-5b37995e45a3Department of Computer Science2008Ditmar, JMcKeever, SWilson, AThis paper discusses a pair of synthesis algorithms that optimise a SystemC design to minimise area when targeting FPGAs. Each can significantly improve the synthesis of a high-level language construct, thus allowing a designer to concentrate more on an algorithm description and less on hardware-specific implementation details. The first algorithm is a source-level transformation implementing function exlining—where a separate block of hardware implements a function and is shared between multiple calls to the function. The second is a novel algorithm for mapping arrays to memories which involves assigning array accesses to memory ports such that no port is ever accessed more than once in a clock cycle. This algorithm assigns accesses to read/write only ports and read-write ports concurrently, solving the assignment problem more efficiently for a wider range of memories compared to existing methods. Both optimisations operate on a high-level program representation and have been implemented in a commercial SystemC compiler. Experiments show that in suitable circumstances these techniques result in significant reductions in logic utilisation for FPGAs.
spellingShingle Ditmar, J
McKeever, S
Wilson, A
Area Optimisation for Field−Programmable Gate Arrays in SystemC Hardware Compilation
title Area Optimisation for Field−Programmable Gate Arrays in SystemC Hardware Compilation
title_full Area Optimisation for Field−Programmable Gate Arrays in SystemC Hardware Compilation
title_fullStr Area Optimisation for Field−Programmable Gate Arrays in SystemC Hardware Compilation
title_full_unstemmed Area Optimisation for Field−Programmable Gate Arrays in SystemC Hardware Compilation
title_short Area Optimisation for Field−Programmable Gate Arrays in SystemC Hardware Compilation
title_sort area optimisation for field programmable gate arrays in systemc hardware compilation
work_keys_str_mv AT ditmarj areaoptimisationforfieldprogrammablegatearraysinsystemchardwarecompilation
AT mckeevers areaoptimisationforfieldprogrammablegatearraysinsystemchardwarecompilation
AT wilsona areaoptimisationforfieldprogrammablegatearraysinsystemchardwarecompilation