Area Optimisation for Field−Programmable Gate Arrays in SystemC Hardware Compilation

Area Optimisation for Field−Programmable Gate Arrays in SystemC Hardware Compilation

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This paper discusses a pair of synthesis algorithms that optimise a SystemC design to minimise area when targeting FPGAs. Each can significantly improve the synthesis of a high-level language construct, thus allowing a designer to concentrate more on an algorithm description and less on hardware-spe...

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Xehetasun bibliografikoak
Egile Nagusiak:	Ditmar, J, McKeever, S, Wilson, A
Formatua:	Journal article
Argitaratua:	2008

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