Area Optimisation for Field−Programmable Gate Arrays in SystemC Hardware Compilation
This paper discusses a pair of synthesis algorithms that optimise a SystemC design to minimise area when targeting FPGAs. Each can significantly improve the synthesis of a high-level language construct, thus allowing a designer to concentrate more on an algorithm description and less on hardware-spe...
| Main Authors: | , , |
|---|---|
| Format: | Journal article |
| Udgivet: |
2008
|
Search Result 1
Area optimisation for field-programmable gate arrays in SystemC hardware compilation
Udgivet 2008
Journal article