APA引文

Müller, S., Leister, H., Dell, P., Gerteis, N., Kroening, D., & Cap, C. (1999). The impact of hardware scheduling mechanisms on the performance and cost of processor designs. dblp computer science bibliography.

Chicago Style (17th ed.) Citation

Müller, S., H. Leister, P. Dell, N. Gerteis, D. Kroening, and C. Cap. The Impact of Hardware Scheduling Mechanisms on the Performance and Cost of Processor Designs. dblp computer science bibliography, 1999.

MLA引文

Müller, S., et al. The Impact of Hardware Scheduling Mechanisms on the Performance and Cost of Processor Designs. dblp computer science bibliography, 1999.