The impact of hardware scheduling mechanisms on the performance and cost of processor designs
Hardware schedulers supporting out-of-order execution are widespread nowadays. Nevertheless, studies quantifying the impact of schedulers on the performance and cost of processors are rare. The paper tries to close this gap. It turns out that the hardware schedulers can double the performance at a m...
| Hlavní autoři: | , , , , |
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| Médium: | Conference item |
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dblp computer science bibliography
1999
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| _version_ | 1826301771763417088 |
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| author | Müller, S Leister, H Dell, P Gerteis, N Kroening, D |
| author2 | Cap, C |
| author_facet | Cap, C Müller, S Leister, H Dell, P Gerteis, N Kroening, D |
| author_sort | Müller, S |
| collection | OXFORD |
| description | Hardware schedulers supporting out-of-order execution are widespread nowadays. Nevertheless, studies quantifying the impact of schedulers on the performance and cost of processors are rare. The paper tries to close this gap. It turns out that the hardware schedulers can double the performance at a moderate increase (10–24%) in a processor’s gate count. Earlier rearranging of instructions allows for better performance, but it does not guarantee it. The lack of features like forwarding and non-blocking resources can nullify this gain. Despite of its out-of-order dispatch capability, the original Scoreboard scheduler, for example, performs significantly worse than a standard in-order pipeline. The paper also identifies the aspects responsible for this poor performance and quantifies their impact. The single most important aspect is the lack of result forwarding. |
| first_indexed | 2024-03-07T05:37:24Z |
| format | Conference item |
| id | oxford-uuid:e46281fd-d38f-47f0-a91e-f52dce5f500f |
| institution | University of Oxford |
| last_indexed | 2024-03-07T05:37:24Z |
| publishDate | 1999 |
| publisher | dblp computer science bibliography |
| record_format | dspace |
| spelling | oxford-uuid:e46281fd-d38f-47f0-a91e-f52dce5f500f2022-03-27T10:16:12ZThe impact of hardware scheduling mechanisms on the performance and cost of processor designsConference itemhttp://purl.org/coar/resource_type/c_5794uuid:e46281fd-d38f-47f0-a91e-f52dce5f500fSymplectic Elements at Oxforddblp computer science bibliography1999Müller, SLeister, HDell, PGerteis, NKroening, DCap, CErhard, WKoch, WHardware schedulers supporting out-of-order execution are widespread nowadays. Nevertheless, studies quantifying the impact of schedulers on the performance and cost of processors are rare. The paper tries to close this gap. It turns out that the hardware schedulers can double the performance at a moderate increase (10–24%) in a processor’s gate count. Earlier rearranging of instructions allows for better performance, but it does not guarantee it. The lack of features like forwarding and non-blocking resources can nullify this gain. Despite of its out-of-order dispatch capability, the original Scoreboard scheduler, for example, performs significantly worse than a standard in-order pipeline. The paper also identifies the aspects responsible for this poor performance and quantifies their impact. The single most important aspect is the lack of result forwarding. |
| spellingShingle | Müller, S Leister, H Dell, P Gerteis, N Kroening, D The impact of hardware scheduling mechanisms on the performance and cost of processor designs |
| title | The impact of hardware scheduling mechanisms on the performance and cost of processor designs |
| title_full | The impact of hardware scheduling mechanisms on the performance and cost of processor designs |
| title_fullStr | The impact of hardware scheduling mechanisms on the performance and cost of processor designs |
| title_full_unstemmed | The impact of hardware scheduling mechanisms on the performance and cost of processor designs |
| title_short | The impact of hardware scheduling mechanisms on the performance and cost of processor designs |
| title_sort | impact of hardware scheduling mechanisms on the performance and cost of processor designs |
| work_keys_str_mv | AT mullers theimpactofhardwareschedulingmechanismsontheperformanceandcostofprocessordesigns AT leisterh theimpactofhardwareschedulingmechanismsontheperformanceandcostofprocessordesigns AT dellp theimpactofhardwareschedulingmechanismsontheperformanceandcostofprocessordesigns AT gerteisn theimpactofhardwareschedulingmechanismsontheperformanceandcostofprocessordesigns AT kroeningd theimpactofhardwareschedulingmechanismsontheperformanceandcostofprocessordesigns AT mullers impactofhardwareschedulingmechanismsontheperformanceandcostofprocessordesigns AT leisterh impactofhardwareschedulingmechanismsontheperformanceandcostofprocessordesigns AT dellp impactofhardwareschedulingmechanismsontheperformanceandcostofprocessordesigns AT gerteisn impactofhardwareschedulingmechanismsontheperformanceandcostofprocessordesigns AT kroeningd impactofhardwareschedulingmechanismsontheperformanceandcostofprocessordesigns |