The impact of hardware scheduling mechanisms on the performance and cost of processor designs - Müller, S; Leister, H; Dell, P; Gerteis, N; Kroening, D (dblp computer science bibliography, 1999)
Hardware schedulers supporting out-of-order execution are widespread nowadays. Nevertheless, studies quantifying the impact of schedulers on the performance and cost of processors are rare. The paper tries to close this gap. It turns out that the hardware schedulers can double the performance at a moderate increase (10–24%) in a processor’s gate count. Earlier rearranging of instructions allows for better performance, but it does not guarantee it. The lack of features like forwarding and non-blocking resources can nullify this gain. Despite of its out-of-order dispatch capability, the original Scoreboard scheduler, for example, performs significantly worse than a standard in-order pipeline. The paper also identifies the aspects responsible for this poor performance and quantifies their impact. The single most important aspect is the lack of result forwarding.