The impact of hardware scheduling mechanisms on the performance and cost of processor designs

Hardware schedulers supporting out-of-order execution are widespread nowadays. Nevertheless, studies quantifying the impact of schedulers on the performance and cost of processors are rare. The paper tries to close this gap. It turns out that the hardware schedulers can double the performance at a m...

詳細記述

書誌詳細
主要な著者:	Müller, S, Leister, H, Dell, P, Gerteis, N, Kroening, D
その他の著者:	Cap, C
フォーマット:	Conference item
出版事項:	dblp computer science bibliography 1999

The Impact of Hardware Scheduling Mechanisms on the Performance and Cost of Processor Designs. 著者: Mueller, S, Leister, H, Dell, P, Gerteis, N, Kroening, D

出版事項 1999

Conference item

The impact of hardware scheduling mechanisms on the performance and cost of processor designs

The Impact of Hardware Scheduling Mechanisms on the Performance and Cost of Processor Designs. 著者: Mueller, S, Leister, H, Dell, P, Gerteis, N, Kroening, D

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