Cytowanie według stylu APA (wyd. 7)

Jain, H., Kroening, D., Sharygina, N., & al., E. (2008). Word-level predicate-abstraction and refinement rechniques for verifying RTL Verilog. Institute of Electrical and Electronics Engineers.

Cytowanie według stylu Chicago (wyd. 17)

Jain, H., D. Kroening, N. Sharygina, i E. al. Word-level Predicate-abstraction and Refinement Rechniques for Verifying RTL Verilog. Institute of Electrical and Electronics Engineers, 2008.

Cytowanie według stylu MLA (wyd. 9)

Jain, H., et al. Word-level Predicate-abstraction and Refinement Rechniques for Verifying RTL Verilog. Institute of Electrical and Electronics Engineers, 2008.