Dyfyniad APA

Jain, H., Kroening, D., Sharygina, N., & al., E. (2008). Word-level predicate-abstraction and refinement rechniques for verifying RTL Verilog. Institute of Electrical and Electronics Engineers.

Dyfyniad Arddull Chicago

Jain, H., D. Kroening, N. Sharygina, and E. al. Word-level Predicate-abstraction and Refinement Rechniques for Verifying RTL Verilog. Institute of Electrical and Electronics Engineers, 2008.

Dyfyniad MLA

Jain, H., et al. Word-level Predicate-abstraction and Refinement Rechniques for Verifying RTL Verilog. Institute of Electrical and Electronics Engineers, 2008.

Rhybudd: Mae'n bosib nad yw'r dyfyniadau hyn bob amser yn 100% cywir.