APA aipamena

Jain, H., Kroening, D., Sharygina, N., & al., E. (2008). Word-level predicate-abstraction and refinement rechniques for verifying RTL Verilog. Institute of Electrical and Electronics Engineers.

Chicago Style aipamena

Jain, H., D. Kroening, N. Sharygina, and E. al. Word-level Predicate-abstraction and Refinement Rechniques for Verifying RTL Verilog. Institute of Electrical and Electronics Engineers, 2008.

MLA aipamena

Jain, H., et al. Word-level Predicate-abstraction and Refinement Rechniques for Verifying RTL Verilog. Institute of Electrical and Electronics Engineers, 2008.