Jain, H., Kroening, D., Sharygina, N., & al., E. (2008). Word-level predicate-abstraction and refinement rechniques for verifying RTL Verilog. Institute of Electrical and Electronics Engineers.
शिकागो शैली (17वां संस्करण) प्रशस्ति पत्रJain, H., D. Kroening, N. Sharygina, और E. al. Word-level Predicate-abstraction and Refinement Rechniques for Verifying RTL Verilog. Institute of Electrical and Electronics Engineers, 2008.
एमएलए (9वां संस्करण) प्रशस्ति पत्रJain, H., et al. Word-level Predicate-abstraction and Refinement Rechniques for Verifying RTL Verilog. Institute of Electrical and Electronics Engineers, 2008.
चेतावनी: ये उद्धरण हमेशा 100% सटीक नहीं हो सकते हैं.