| Summary: | This paper presents the performance of Radix-4 Modified Booth Algorithm. Booth algorithm is a multiplication algorithm
that multiplies two signed binary numbers in two's complement notation. Multiplier is a fundamental component in
general-purpose microprocessors and in digital signal processors. With advances in technology, researchers design
multipliers which offer high speed, low power, and less area implementation. Booth multiplier algorithm is designed to
reduce number of partial products as compared to conventional multiplier. The proposed design is simulated by using
Verilog HDL in Quartus II and implemented in Cyclone II FPGA. The result shows that the average output delay is
20.78 ns. The whole design has been verified by gate level simulation.
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